In contrast to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs), which are fabricated using conventional lithographic fabrication methods, non-planar FETs incorporate various vertical transistor structures. One such semiconductor structure is the “FinFET,” which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels, and which are typically on the order of tens of nanometers in width.
More particularly, referring to the exemplary prior art nonplanar FET structure shown in FIG. 1, a FinFET 100 generally includes two or more parallel silicon fin structures (or simply “fins”) 104 and 106. These structures are typically formed using a silicon-on-insulator (SOI) substrate (not shown) or alternatively on a bulk substrate, with fins 104 and 106 extending between a common drain electrode and a common source electrode (not shown). A conductive gate structure 102 “wraps around” three sides of both fins 104 and 106, and is separated from the fins by a standard gate oxide layer 103. While FIG. 1 illustrates only one gate structure 102 wrapped around fins 104 and 106, two, three or more parallel gate structures can be wrapped around the fins. Fins 104 and 106 may be suitably doped to produce the desired FET polarity, as is known in the art, such that a gate channel is formed within the near surface of the fins adjacent to gate oxide 103. The width of the gate, indicated by double-headed arrow 108, determines the effective channel length of the device.
Current scaling of MOSFET dimensions leads to the need to integrate a 3-D FinFET structures into many integrated circuit (IC) designs. Embedded epitaxy for source/drain formation must also take a 3-D shape, in one example, for static random access memory (SRAM) scaling requirements. The spacers are formed in 3-D and are prone to variation induced by fin and dummy poly gate shapes. It is further difficult to control silicide formation in a 3-D technology with intentional topography, aggravated by the presence of multiple crystal planes as well as non-uniform spacer profile across the gate-source/drain interface.
In addition, performance and scaling requires the fin height to increase and the fin pitch to decrease in future nodes. An increase in fin height increases the width of the device, but the smaller fin pitch decreases the area of the contact that can be made around the device. At the same time, the smaller gate pitch further decreases the contact size. As such, to make further advances in scaling, better contact-active resistance is required and/or an increase in device stress is required.
To further reduce scale in an SRAM in future nodes, it is desirable to block the epitaxial source/drain (S/D) components from the fins, and rely only on the fins themselves as the S/D. The SRAM transistor in such a device using currently known methods, however, would have unacceptably high contact resistance if a conventional silicide were formed. A contact liner that has the properties of not consuming the fins as well as delivering band-edge low Schottky barrier height properties would make such a scheme possible.
Existing solutions known in the art have attempted to merge the fins together, and have the silicide only from the top. That is, existing solutions known in the art have attempted to transform the 3-D problem into a known 2-D problem. However, merging the fins requires extra space in the SRAM to separate the n-type metal oxide semiconductor (NMOS) from the p-type metal oxide semiconductor (PMOS). This severely increases the silicon area to manufacture a chip. Also, contacting only from the top in 2-D rather than wrapping the contact around in 3-D severely decreases the contact area, thus increasing the contact-active resistance substantially and reducing device performance.
Accordingly, it is desirable to provide FinFET structures and methods for fabricating FinFET structures that incorporate a scheme in which dual band-edge metals or metal compounds can be integrated into a self-aligned contact scheme. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings, the brief summary, and this background of the invention.